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mystery of the depleted coin cell

The mystery of the depleted coin cell

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The mystery of the depleted coin cell

Thomas Kuehl

Feb 11 2014 09:22 AM

Comments 6

Monitoring the voltage level of a coin cell in a portable device or in
back-up service is a common, simple application for modern CMOS operation
amplifiers (op amps).

Figure 1 shows an implementation using the 1.8-V, OPA333 zero-drift op amp. The coin cell has a voltage of 3
V, while the circuit is powered by a 3- to 5-V level.

Oddly, I’ve had customers report that the circuit drains the coin cell long
before the expected life; in just a matter of days, or even hours! These
customers found when the op amp was removed, the coin cell remained charged.
That piqued my curiosity, and I began an investigation to find out what was
happening.

Figure 1 - OPA333 unity-gain amplifier connected to monitor coin cell
voltage

A popular coin cell, the lithium CR2032, is rated at 175 mAh capacity and 200
uA continuous current. The OPA333 input bias current is typically 70 pA. That alone
wouldn’t deplete the cell for years. Something else was draining the
battery.  A close look at the OPA333 internal schematic revealed a plausible discharge
scenario.

Figure 2 shows a block diagram of the amplifier core and its input ESD
protection. Remember that most ICs are protected against ESD during
out-of-circuit handling. The ESD cells are designed to be off under normal
operating conditions.

The OPA333 ESD input protection has low-leakage steering diodes
connected from each input, to the supply lines. An ESD clamp connects between
those lines. These diodes are normally reversed biased. However, if the supply
voltage V+ is turned off, becoming high impedance, diode D3 can become forward
biased. Then, the amplifier core and anything else connected to V+ can drain
current from the coin cell.

The OPA333 quiescent current is only 17 uA, so it is probable
other components connected to the +V supply line were drawing current too.

Figure 2 - Internal block diagram shows current path
through D3 from the non-inverting input to +V supply line

Some op amps have a shut-down pin. When in that mode, they draw a tiny amount
of supply current. However, if the ESD cell uses the Figure 2 design, the diode
can still conduct current.

The solution is to employ an op amp with a different ESD cell design.

Figure 3 shows the ESD cell design used in the TLV2450 rail-to-rail input/output op amp. It uses a fast,
low-leakage clamp - similar to a zener diode. It turns on fast and limits
applied voltages to a safe level during an ESD event. There is no internal
current path to the VDD pin.

Figure 3 - The TLV2450 uses an input ESD clamp. There is no internal
current path from the input to the VDD pin.

It may be difficult for an engineer to determine the ESD cell design an
amplifier uses. One hint can be found in the amplifier’s data sheet. When you
look at the Absolute Maximum Ratings, if the signal input has a range listed,
such as -0.3 V to (V+) + 0.3 V, the 0.3 V is a limit that assures the ESD diodes
remain off. Any higher, and they may turn on.

If in doubt, visit our Precision Amplifiers Forum here in the E2E™ Community
and submit a question. One of our Applications Engineers will research it for
you.

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$post.CommentCount)

Difference
Amplifier, Fully
Differential Amplifier, General
Purpose Amplifier, High
Output Current Amplifier (>=50mA), High
Supply Voltage Amplifier (>=30V), Instrumentation
Amplifier, Low
Input Bias Current Amp (<=10pA), Low
Noise Amp (<=10nV/rtHz), Low
Offset Voltage Amplifier (<=500uV), Low
Power Amp (<=500uA), Low
Supply Voltage Amplifier (<=2.7V), Precision
Amplifier, Zero
Drift Precision Amplifier, OPA333,
TLV2450

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Comments

Deepak
murali

Feb 12 2014 04:00 AM

Nice blog. Do you mean than in TLV2450, ESD prtection is not available for
input voltage greater than VDD ?

Thomas
Kuehl

Feb 12 2014 09:30 AM

Hi Deepak,

The ESD protection is in place and effective against out-of-circuit ESD
events. Those voltage levels far exceed the normal in-circuit VDD levels. The
ESD cells should remain completely off under normal operating conditions when
VDD is present.

Thomas

Ahmet
Cetin

Feb 21 2014 14:32 PM

Good experience Thank you.

Thomas
Kuehl

Feb 21 2014 14:54 PM

Ahmet,

You are welcome.

Regards, Thomas

Jason
Mitchell1

Mar 10 2014 02:24 AM

Without even knowing what the insides of the op-amp look like I could have
predicted this would happen.

Many years ago as a student, I had a similar situation with logic devices
and older JFET op-amps. In those cases it was simple to deduce there was
leakage into VCC.

In this case it is as clear as day its the ESD diodes. This also happens
with A/D converter inputs on microcontrollers where a battery is monitored.
What I usually do is ensure the measurement path has the highest possible
impedance to ensure the battery doesn't get drained at all.

Thomas
Kuehl

Mar 10 2014 09:48 AM

Hello Jason,

Thanks for reading and your comments.

Yes indeed cell discharge can occur with other analog ICs if they use the
same kind of input ESD cell circuitry. We have had reports of very low power
A/D converters draining a cell through their input and found the same cause at
work.

Regards, Thomas

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