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A Little Pad In That Via

Here's an interesting via-in-pad situation we ran across a while ago. I'm not
sure what the chip is. Probably a processor or an FPGA that generates a bit of
heat.

The intention with the layout was on the right track. However, the
implementation wasn't really workable. All of those big vias were put there to
sink heat away from the thermal pad on the bottom of the chip. The vias being so
large, heat would be removed by air convection as well as conduction through the
via walls. The thought is good.

In practice though, there are a couple of big problems with this approach.
First, the pad on the PCB is much larger than the pad on the chip and the extra
area is not masked. Even without the vias, that could make for more difficult
solder control. The biggest problem is simply the large open vias. It really
isn't possible to solder such a layout with standard surface mount process.
Since this is a prototype, we found a way to make it work, but for volume
manufacturing, as well as for cost reduction in the prototype, a different
approach is needed.

In the second image here, we've simulated what a good workable footprint
could look like. This isn't the only possible way to do it, but it would work
well. Here, the exposed pad matches the size of the heat slug on the chip. The
rest of the pad is still there for thermal conduction but it is masked off.
There are a generous number of thermal vias in the masked area and a few capped
vias in the solder area. Even better would be to plug and copper-plate over the
vias in the solder area, but this way works too and is less expensive at the
board fab house.

Duane Benson
Flying spaghetti monster says what?

Posted on November 27, 2007 in QFN
and DFN , Via
in Pad

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