Subject: PCB Stack-Up - Part 5
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Henry Ott
Consultants
Electromagnetic Compatibility Consulting and
Training

PCB Stack-Up

Part 5. Ten-Layer Boards

A ten-layer board should be used when six routing layers are
required.  Ten-layer boards, therefore, usually have six signal layers and
four planes.  Having more than six signal layers on a ten-layer board is
not recommended.  Ten-layers is also the largest number of layers
that can usually be conveniently fabricated in a 0.062" thick board.
Occasionally you will see a twelve-layer board fabricated as a 0.062" thick
board, but the number of fabricators capable of producing it are limited..

High layer count boards (ten +) require thin dielectrics (typically 0.006" or
less on a 0.062" thick board) and therefore they automatically have tight
coupling between layers.  When properly stacked and routed they can meet
all of our objectives and will have excellent EMC performance and signal
integrity.

A very common and nearly ideal stack-up for a ten-layer board is shown in
Figure 12.  The reason that this stack-up has such good performance is the
tight coupling of the signal and return planes, the shielding of the high-speed
signal layers, the existence of multiple ground planes, as well as a tightly
coupled power/ground plane pair in the center of the board.  High-speed
signals normally would be routed on the signal layers buried between planes
(layers 3-4 and 7-8 in this case).

________________Signal (low-speed signals)

________________Gnd.
________________Signal (high-speed signals
& clocks)
________________Signal (high-speed signals &
clocks)

________________Pwr.
Figure 12
________________Gnd.

________________Signal (high-speed signals & clocks)

________________Signal (high-speed signals & clocks)

________________Gnd. or Pwr.
________________Signal (low-speed
signals)

The common way to pair orthogonally routed signals in this configuration
would be to pair layers 1 & 10 (carrying only low-frequency signals), as
well as pairing layers 3 & 4, and layers 7 & 8 (both carrying high-speed
signals).  By paring signals in this manner, the planes on layers 2 and 9
provide shielding to the high-frequency signal traces on the inner layers.
In addition the signals on layers 3 & 4 are isolated from the signals on
layers 7 & 8 by the center power/ground plane pair.  For example,
high-speed clocks might be routed on one of these pairs, and high-speed address
and data buses routed on the other pair.  In this way the bus lines are
protected, against being contaminated with clock noise, by the intervening
planes.

This configuration satisfies all of the five original objectives.

Another possibility for routing orthogonal signals on the ten-layer board
shown in Fig. 12 is to pair layers 1 & 3, layers 4 & 7, and layers 8
& 10.   In the case of layer pairs 1 & 3 as well as 8 &
10, this has the advantage of routing orthogonal signals with reference to the
same plane.  The disadvantage, of course, is that if layers 1 and/or 10
have high frequency signals on them there is no inherent shielding provided by
the PCB planes.  Therefore, these signal layers should be placed very close
to their adjacent plane (which occurs naturally in the case of a ten-layer
board).

Each of the routing configurations discussed above has some advantages and
some disadvantages, either can be made to provide good EMC and signal integrity
performance if laid out carefully.

The stack-up in Fig. 12 can be further improved on by the use of some form of
embedded
PCB capacitance technology (e.g. Zycon Buried Capacitanceú ) for layers
5 and 6, thereby improving the high-frequency power/ground plane decoupling,

Fig. 13 shows another possible stack-up for a ten-layer board.

________________Ground/Mounting Pads

________________Signal (H1)
________________Signal (V1)

________________Ground
________________Signal
(H2)
Figure 13
________________Signal (V2)

________________Power
________________Signal (H3)

________________Signal (V3)
________________Ground/Mounting pads
if double sided surface mount

This configuration gives up the closely spaced power/ground plane pair.
In return it provides three signal- routing-layer pairs shielded by the ground
planes on the outer layers of the board, and isolated from each other by the
internal power and ground plane.  All signal layers are shielded and
isolated from each other in this configuration.  The stack-up of Fig. 13 is
very desirable if you have very few low-speed signals to put on the outer signal
layers (as in Fig. 12) and most of  your signals are high-speed, since it
provides three pairs of shielded signal routing layers.

One concern with this stack-up relates to how badly the outside ground planes
will be cut-up by the component mounting pads and vias on a high density
PCB.   This issue has to be addressed and the outside layers carefully
laid out.

This configuration satisfies objectives 1, 2, 4, and 5, but not 3.

A third possibility is shown in Fig. 14.  This stack-up allows the
routing of orthogonal signals adjacent to the same plane, but in the process
also has to give up the closely spaced power/ground planes.  This
configuration is similar to the eight-layer board shown in Fig. 10, with the
addition of the two outer low-frequency routing layers.

________________Signal (low-speed signals)

________________Pwr.
________________Signal (H1)

________________Gnd.
________________ Signal
(V1)
Figure 14
________________ Signal (H2)

________________Gnd.
________________Signal (V2)

________________Gnd. or Pwr.
________________Signal (low-speed
signals)

The configuration in Fig. 14 satisfies objectives 1, 2, 4, and 5, but not
3.  It, however, has the additional advantage that orthogonal routed
signals always reference the same plane.

The stack-up in Fig. 14 can be further improved by the use of some form of
embedded
PCB capacitance technology (e.g. Zycon Buried Capacitanceú ) for layers
2 and 9 (thereby satisfying objective 3).  This, however, effectively
converts it to a twelve-layer board.

Summary

The previous sections have discussed various ways to stack-up high-speed,
digital logic, PCBs having from four to ten layers.  A good PCB stack-up
reduces radiation, improves signal quality, and helps aid in the decoupling of
the power bus.  No one stack-up is best, there is a number of viable
options in each case and some compromise of objectives is usually necessary.

In addition to the number of layers, the type of layer (plane or signal), and
the ordering of the layers, the following factors are also very important in
determining the EMC performance of the board:

The layer spacing.

The assigning of signal layer pairs for orthogonal routing of
signals.

The assignment of signals (clock, bus, high-speed, low-frequency, etc.) to
which signal-routing-layer pairs.

This discussion on board stack-up has assumed a standard 0.062" thick
board, with symmetrical cross-section, and conventional via
technology.   If  blind, buried, or micro vias are considered,
other factors come into play and additional board stack-ups not only become
possible but in many cases desirable.

© 2002 Henry W.
Ott
Henry Ott Consultants,  48 Baker Road  Livingston,  NJ
07039  (973) 992-1793

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Henry Ott Consultants
48 Baker Road Livingston, NJ 07039
Phone: 973-992-1793,   FAX: 973-533-1442
June
14, 2002