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Timing is Everything: Jitter specifications

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Timing is Everything: Jitter specifications

Gabe Ayala

Aug 29 2014 10:00 AM

Comments 0

Welcome back to Timing is Everything! Last time we covered Understanding PLL loop filter response. Today, I will be
helping you learn how to better understand the variety of jitter
specifications.

As timing requirements in high-speed applications become
tighter and more stringent, a more developed understanding of the various jitter
specifications is highly essential; from 10 Gbit Ethernet networks to high-speed
interconnects such as PCIe, robustness implied in the links is closely tied to
reducing timing margins.

In short, jitter is the deviation of signal edges from an “ideal” value or
interval.  Using a periodic signal as our ideal reference, a “real” signal
in a system with noise contributions from sources such as power supplies,
thermal noise, and cross coupling interferences is more accurately described in
the images below. Figure 1 is the “ideal” signal, with the frequency domain
representation of the signal also shown.

Figure 1: The “ideal” signal

As noise and perturbations affect the signal, the resultant waveform
undergoes the effect of jitter, as shown in Figure 2. The spreading of the
signal's energy across the frequency spectrum is known as phase noise.

Figure 2: Effects of jitter

Jitter can be further broken down into several subclasses and specifications,
each with its own properties and measurement techniques. The major measurement
techniques are as follows: period jitter, cycle-to-cycle period jitter and phase
jitter. While these are not all of the forms of measurement, we will focus on
only these in this short dissection.

Period Jitter

Period jitter is the deviation of cycle duration with respect to the
aforementioned ideal signal's period. By randomly selecting a number of cycles,
we can then calculate the average clock period (which should approach the ideal
period’s duration) as well as the standard deviation and peak-to-peak values.
The standard deviation is referred to as the “RMS jitter” and the peak-to-peak
value is referred to as the “Pk-Pk period jitter.”

Because of period jitter’s random Gaussian distribution, its energy contents
are fully described by the mean and standard deviation; however, a more useful
measurement is derived from the Pk-Pk period jitter. Knowing the Pk-Pk period
jitter is useful when appropriately configuring system setup and hold times. The
following equation approximates this worst case scenario:

Pk-Pk period jitter = 2σ x (RMS period jitter)

The appropriate value of σ is derived from the Gaussian distribution
probability density function, shown in Table 1. The table reads as follows: for
a given sample size N cycles, N-1 of those samples cycles will be
have a period within σN of the mean value of the distribution.
Only then will one cycle of N cycles fall outside of that range. Bit
Error Rate is used directly where BER = 1/N.

Table 1: Gaussian distribution probability

Cycle-to-Cycle Jitter

Cycle-to-cycle jitter is the variation of the cycle time of two adjacent
cycles in a periodic signal. The adjacent cycles are randomly chosen throughout
the signal stream until enough samples have been collected – typically 1,000+
samples. The peak deviation in the adjacent cycle sets is reported as
cycle-to-cycle jitter and is especially useful in spread spectrum clocking where
period jitter is highly susceptible to intentional frequency spreading.

Phase Jitter and Phase Noise

When looking at the frequency domain representation of the signal of
interest, noise values at specific offset frequencies (with respect to the
carrier) are known as the phase noise. An example of this -110 dBc/Hz at 12 MHz
offset or -70 dBc/Hz at 50 kHz offset.

Taking the discrete phase noise points over a band of interest and
integrating results in the phase jitter of a signal is described in the equation
below. Here, f0 is the carrier and f1
and f2 are the limits of the integration bandwidth on only
one side of the carrier (it is assumed the signal is symmetric).

The importance of this measurement is similar to that of periodic jitter,
only here the distribution of periods is generated by their respective
frequencies (hence the wider spread of energy in both Figures 1 and 2). With
respect to the communications systems as well as ADCs and DACs, both receiver
and transmitter in conjunction create a band-pass-filter for through which
acceptable noise figure of merit can be created.

Time Interval Error (TIE)

Time Interval Error refers to the time deviation of the measured signal with
respect to an “ideal” signal. Figure 3 shows how TIE is measured. Here, the
“ideal” signal period is typically generated by the measurement device from the
average period of the signal of interest. TIE is calculated as follows:

TIE measurements are
useful in applications in which the reference clock is recovered from a data
stream using a CDR (Clock/Data Recovery) circuit. Large TIE values are good
indicators that the recovered clock PLL is unable to keep up with change in the
signal data rate.

Figure 3: Time Interval Error
measurement

Thanks
for joining me on Timing is Everything! I hope you now have a better
understanding of jitter specifications. Please leave any questions or comments
about material covered in this post below, or head to the Clock and Timing Forum
in TI’s E2E™ Community to get your specific application need or question
addressed!

Additional
resources:

Learn more about the clock and timing portfolio.

Read more Timing is Everything blogs, including how to measure additive jitter.

Check out WEBENCH® Clock Architect and Clock Design Tool for additional design tools.

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