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> | # Basic SSI Timing The timing relationship between FS512 (out) and SSI_CLK is: Where an SSI_CLK edge follows an FS512 edge by 0.0 to 5.0 ns. Likewise, FS1 follows a FS512 edge by 0.0 to 10.0 ns. Note: The SSI_CLK and FS1 might be synchronized with the either the falling edge or the rising edge of FS512. Which edge is impossible to predict since it depends on power up timing. The timing relationship for serial port data and FS1 with respect to the SSI_CLK are: Setup times for SSI_DIN and FS1 are 5.0 ns with a hold time of 0.0 ns with the edge of SSI_CLK. Clock to output times for SSI_DOUT is 0.0 to 12.0ns from the edge of SSI_CLK. Which edge of SSI_CLK is used depends on the SSICLK_Edge bit in the SSI configuration register. The SSI_CLK can operate as an input or an output. Normally, it operates as an output, but under some rare situations it is more useful as an input. When used as an input, the SSI clock can be intermittent, gated, etc. Just remember that both the falling and rising edges of the SSI clock are used. The minimum clock period for the SSI clock is 20 ns, with a 10 ns minimum clock low or clock high period. ## "Normal" SSI Port Configuration In a normal SSI port configuration, the SSI configuration register is set up as follows. MSB Skew = 2 FS1 Skew = 1 SSI Clk Invert = 0 SSI Clk Edge = 0 FS1 OE = 1 SSI Clk OE = 1 SSI Clk Select = anything The timing of the first few bits looks like the diagram below. Each SSI audio channel uses 32 bits of data, with the LSB left justified and in sync with FS1. The unused eight bits are ignored on SSI_DIN and output as zeros on SSI_DOUT. Data changes on the rising edge of SSI_CLK and is sampled on the falling edge. The internal phase counter is reset to zero on the MSB of the first audio channel. ## I2S SSI Port Configuration I2S mode differs from "normal" mode in that 1FS comes one bit period before the MSB and the SSI Clock is inverted. Register Configuration for this mode is more complicated than the normal mode.
> Bit Rate | 64 fs | 128 fs | 256 fs | 512 fs
> MSB Skew | 2 | 2 | 2 | 2
> FS1 Skew | 17 | 9 | 5 | 3
> SSI Clk Edge | 1 | 1 | 1 | 1
> SSI Clk Invert | 1 | 1 | 1 | 1
> SSI Clk Select | 000 | 001 | 010 | 011
The internal phase counter is reset to zero on the MSB of the first audio channel-- not with the edge of FS1.
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